The present invention relates to a MOS (metal oxide semiconductor) type semiconductor device with a gate protecting circuit for protecting an internal circuit.
A MOS type semiconductor device containing a MOS FET (metal oxide semiconductor field effect transistor) typically has a low withstanding voltage (that is, the ability to withstand a static discharge) normally in the range of 20 V-100 V, because the input impedance of the MOS FET is extremely high and the thickness of the gate insulation film is thin, typically 400 .ANG. to 1000 .ANG.. For this reason, the gate insulation film is easily destroyed by static electricity generated by friction and the like. To protect the gate insulation film from destruction by static electricity, the typical MOS type semiconductor device is provided with a gate film protecting circuit.
The basic construction of a MOS type semiconductor device with the gate film protecting circuit will be described referring to FIG. 1. A MOS FET Q1 constitutes a part of internal circuit 11. A resistor R made of an impurity diffusion layer is inserted between the gate of the MOS FET Q1 and the input terminal (bonding pad) 12. A MOS FET Q2 is connected between the gate of the MOS FET Q1 and a low potential power source V.sub.SS. The gate of the MOS FET Q2 is connected to the power source V.sub.SS. The resistor R and the MOS FET Q2 constitute a gate film protecting circuit 13.
In this circuit, when an over-voltage with a sharp pulse waveform, such as a surge voltage, is applied to the input terminal, the over-voltage passes through the resistor R. The over-voltage is then clamped by the break down or foward bias characteristics of the PN junction located between the resistor R and the semiconductor substrate and the waveform is smoothed by the resistivity of the resistor R. The high voltage then enters the diffusion layer of the MOS FET Q2 where its amplitude is reduced through action of the low potential power source V.sub.SS being applied to the gate electrode of the MOS FET Q2, which causes the electric field at the surface of the substrate to increase and thus to reduce the over-voltage. In this way, the amplitude-reduced voltage is applied to the input section of the internal circuit 11, more exactly the gate of the MOS FET Q1, and the internal circuit is protected from the extremely high over-voltage.
FIG. 2 shows a pattern diagram of the circuit shown in FIG. 1. In FIG. 2, a wiring layer 12a made of aluminum, for example, connects the bonding pad 12, the input terminal, and an impurity diffusion layer which constitutes a protecting resistive layer 15. An input diffusion layer 14 with a contact hole CH provides a contact between the wiring layer 12a and the protecting resistive layer 15. The resistive layer 15, with resistance of approximately 500 ohms to several kilohms, provides a time constant from 1 ns to 5 ns for passing the over-voltage. With this time constant, the waveform of the over-voltage is made smoother, i.e., sharp peaks are reduced.
With advances in the microfabrication technique of manufacturing integrated circuits, the thickness of the gate insulation film has become thinner and the depth of the diffusion layer has become shallower. Because of these reductions, the gate protecting circuit is easily defeated by a relatively small surge voltage. Thus, the internal circuit is unsatisfactorily protected from the over-voltage.